1. Field of the Invention
The present invention relates generally to a communications interface and, in particular, to a multipurpose bus interface circuit which uses as a digital signal processor to provide a communications interface between, for example, a personal computer and a command/response, time division multiplexing data bus such as, for example, a Military Standard 1553 multiplex data bus.
2. Description of the Prior Art
Military Standard 1553 contains requirements for military aircraft command/response, time division multiplexing data bus techniques utilized in systems integration of military aircraft systems such as avionics and electronic warfare systems. This Military Standard applies to a variety of military aircraft such as the F-14 and the F/A-18. The multipurpose communications interface of the present invention is particularly adapted for use with data buses where Military Standard 1553 applies, but may also be adapted for use to interface other data buses such as the RS-232 interface used to communicate with, for example, general purpose computer equipment.
In the prior art there are multipurpose interfaces which provide the means for communicating on a Military Standard 1553 avionics bus or the like. One such device of the prior art is a "Multipurpose Bus Interface" disclosed in U.S. Pat. No. 5,001,704. The multipurpose bus interface of U.S. Pat. No. 5,001,704 includes a main controller for controlling the transfer of data between a first bus and a RAM. A microstore contains the software for the main controller, the software controlling the handling and interpretation of data to and from the first bus. A co-processor has direct access to the RAM and performs the data processing function of the interface circuit. An interface module provides interface between the RAM and a second data bus, the interface module formatting the data transmitted between the RAM and the second data bus.
While satisfactory for its intended purpose that of providing a means for interfacing a first communications bus to a second communications bus where at least one of the buses is a command response multiplexing data bus, this prior art device is complex in design and does not perform all of the functions of the present invention. Further, the present invention makes use of a combination of electrical components controlled by a digital signal processor utilizing a unique computer software program that is somewhat different from that of the prior art U.S. Pat. No. 5,001,704.